Display data RAM (DDRAM) becomes increasingly important along with rapid growth of display techniques. A DDRAM is built in a display device and an access speed of the DDRAM greatly affects performance of the display device.
To increase access speed, DDRAM frequently controls an order of operations through an arbiter. In other words, when so-called collisions occur due to simultaneous write/read operations, the arbiter appropriately arranges a processing sequence of the operations, usually by delaying some of the operations.
FIG. 1 shows a timing diagram of signals in a conventional display device. For example, an arbiter generates a set of output signals WREQ_Q, DREQ_A and ADR_A according to a set of input signals WREQ, WADR, DREQ and DADR. The write signal WREQ and the address signal WADR are for write operations. The display signal DREQ and the address signal DADR are for display operations. In this example, as indicated by the address signal ADR_A generated by the arbiter, the write operation occupies two write/read cycles of the arbiter, e.g., a period P1. The display operation occupies three write/read cycles of the arbiter, e.g., a period P2. At a time point t1, a pulse occurs in the write signal WREQ, and in response to an address [0] assigned by the write address signal WADR, the arbiter performs the write operation of the address [0]. At a time point t2, a pulse occurs in the display signal DREQ, and in response to an address [a] assigned by the display address signal DADR, the arbiter performs the display operation of the address [a]. However, due to the previous write operation of the address [0] is not completed, a collision is incurred which causes the arbiter to postpone the display operation of the address [a] to a time point t3. Similarly, the write operation of an address [1] is postponed to a time point t4, and the write operation of an address [2] is postponed to a time point t5. However, between the time points t5 and t6, the arbiter is overloaded and the arbiter loses a part of the operations, e.g., the display operation of an address [b] may be lost by the arbiter.
It is concluded from the above description that, the speed of a DDRAM is determined by a write/read cycle of an arbiter when a DDRAM accesses data in a unit of one pixel. Under such conditions, when the arbiter is demanded to write, read or display data in high speed, the arbiter delays the write or read operations due to collisions, which may lead to lose of write or read operations. Further, for a DDRAM having a large capacity, the resistance load is aggravated due to long signal wires, such that not only time margins are reduced but also access failures are likely resulted from the high speed write operations.